IEEE

Evaluation of Multi-Bit Input Logic Blocks in RTL-Designed FPGA Architecture: A Framework for FPGA and ASIC Integration

This paper explores the evaluation and optimization of multi-bit input logic blocks (LBs) within RTL-designed FPGA architectures. Traditional FPGA designs face limitations in power consumption, delay, ...
IEEE

Multi-Bit Successive Cancellation List Decoding of Polar Codes Using One-Bit Error Boundary

Abstract: This letter proposes an efficient method to reduce path splits in the successive cancellation list (SCL) decoding. We construct the boundary consisting of ...