Santa Cruz, Calif. – Claiming the first hybrid approach to transistor-level timing and crosstalk analysis, Nassda Corp. this week will introduce Hanex, a product that combines static and dynamic ...

IR-drop has always been somewhat of an issue in chip design; voltage decreases as current travels along any path with any resistance. Ohm’s Law is likely the first thing that every electrical engineer ...

At one time a relatively infrequent occurrence, voltage drop is now a major impediment to reliability at advanced nodes. Decades ago, voltage drop was only an issue for very large and high-speed ...

Nanometer design will require new thinking in timing closure. Historically, design teams relied on static timing analysis, which depends on the abstracted behavior of individual gates to perform ...

Static Timing Analysis (STA) not only acts as a connecting link between backend and frontend design activities, but more importantly helps in bridging the gap between simulation and silicon. STA is ...

With the increasing size and complexity of FPGA devices, there is a need for more efficient verification methods. Timing simulation can be the most revealing verification method; however, it is often ...