EDN

MIPS permits user-defined instructions for processor cores

SAN MATEO, Calif. — MIPS Technologies Inc. has entered the race to deliver microprocessor cores that accept custom-made instructions, saying the move gives designers an alternative to hardwired logic ...
Design-Reuse

Development and use of an Instruction Set Simulator of 68000-compatible processor core

This paper presents an instruction set simulator of a 32-bit CPU and explains its use in embedded software development. Interaction of the ISS with transaction level model of a complex peripheral ...
Design-Reuse

ARC introduces 16/32-bit instruction set architecture to reduce memory requirements by up to 30 per cent

ARC's configurable processor adds the ability to run both 16 and 32-bit instructions on a 32-bit architecture, allowing designers to reduce memory requirements by up to 30%, resulting in both lower ...
EDN

Reconfigurable processor combines extensible core with SRAM-based FPGA

This system-chip features an embedded reconfigurable processor built by joining a configurable and extensible processor core and a SRAM-based embedded FPGA. The following article will be presented at ...