JEDEC Advances DDR5 MRDIMM Ecosystem with New Memory Interface Logic and Expanded MRDIMM Roadmap

JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced milestones from its JC-40 and JC-45 Committees for Logic and ...
Electronic Design

Interface Logic Will Never Die

The design community has a love/hate relationship with interface logic. Many designers would like to see it incorporated in ASICs or replaced by some type of programmable gate array at the start of ...
EDN

Interface chips: Between logic and a hard place

Logic signals have fallen from the 15V of the old CMOS 4000 series to 5V TTL (transistor-to-transistor logic) to modern CMOS levels of 3.3, 2.7, and 1.8V. Advanced processes use digital logic that ...
EDN

Virage Logic Extends Comprehensive DDR Interface IP Portfolio with System-Validated DDR3 and New Low Power DDR

FREMONT, Calif., Feb 02, 2009 (BUSINESS WIRE) — Virage Logic Corporation (NASDAQ:VIRL), the semiconductor industry’s trusted IP partner, today announced two key developments that extend its ...
Hackaday

Logic Analyzers: Capabilities And Limitations

Last time, we’ve used a logic analyzer to investigate the ID_SD and ID_SC pins on a Raspberry Pi, which turned out to be regular I2C, and then we hacked hotplug into the Raspberry Pi camera code with ...